1. Field of the Invention
Embodiments of the present invention relate generally to static random access memory (SRAM) design and more specifically to an active bit line charge keeper.
2. Description of the Related Art
Integrated circuits commonly embed SRAM circuits to provide on-chip data storage. A given instance of an SRAM circuit typically includes, without limitation, an array of storage cells, write drivers, write column multiplexers, read column selectors, sense amplifiers, and address decoders. One common type of storage cell is a six-transistor (“6T”) storage cell. A two-dimensional array of 6T storage cells allows one selected row of 6T storage cells to be accessed at a time, either for reading or writing data stored in the selected row. Pairs of bit lines typically provide access to data for each column within the row of 6T storage cells. Each pair of bit lines transmits a differential representation of the data stored within a corresponding 6T cell in the selected row. When data is driven by a low impedance column driver along the pair of bit lines, that data is written into the 6T cell. When the bit lines are not driven, data stored within the 6T cell may be sensed differentially from the pair of bit lines.
Each pair of bit lines is typically shared over a plurality of rows within the two-dimensional array for access to a given column over each row. As a result, access to a given row of data may leave the bit lines in a particular state (residual state) that may need to be overcome for a subsequent access to be successful. For example, a set of “1s” may be read from every element in a first row of 6T storage cells, followed by a write access to a second row of 6T storage cells containing all “0s.” The state of the bit lines after the read access to the first row of 6T storage cells corresponds to all “1s,” thereby requiring the write driver within the SRAM circuit to drive the bit lines through a sufficiently full transition from “1s” to “0s” in order for the data intended to be stored within the second row to be reliably written. The amount of time a bit line pair is subjected to a read or write operation determines the actual voltage swing on the bit line pair. In general, the optimal differential voltage for the bit line pair prior to the a read or write operation is actually much less than the full supply voltage. In fact, when a read or write operation is performed, the voltage levels on the bit line pair may stray too far high or low and become “over developed.” Over developed bit line pairs may cause the SRAM circuit to become unreliable.
Person skilled in the art will recognize that for a given process technology, the upper performance limit of an SRAM circuit is typically defined by the ability of the SRAM circuit to overcome a residual bit line state, which is increasingly difficult at higher performance levels. Thus, as SRAM circuits are required to operate at progressively higher performance levels, reducing the effects of residual bit line state within the SRAM circuits becomes increasingly important as a determining factor of performance.
One solution to reducing the effects of residual bit line state within an SRAM circuit is to always fully restore the state of all bit lines to a known state prior to each access. This process is called “pre-charging.” While pre-charging bit lines before each SRAM access provides reliable access, this technique is also time consuming and therefore potentially detrimental to the overall performance of an SRAM circuit. One approach to improving SRAM performance is to shorten the pre-charge time within the SRAM. However, this approach is highly sensitive to process variation and may result in an unacceptable drop in device yield.
As the foregoing illustrates, what is needed in the art is a technique for improving SRAM performance that is relatively insensitive to process variation.